The present invention relates to a semiconductor chip package, and more particularly to a wafer level chip scale package which has improved reliability against thermal stress.
In order to ensure miniaturization and multi-functionality of electronic products or communication devices, semiconductor packages are required to be of small in size, light weight, multi-pin connection, high speed, and high functionality. In order to meet these requirements, packages are to be of substantially a chip size at a wafer level when manufactured. This type of packages is known as a wafer level chip scale package (WLCSP).
FIG. 1 is a cross-sectional view illustrating a conventional WLCSP. The WLCSP 100 includes: a semiconductor chip 110 having a plurality of edge pads 120; a lower insulation layer 130 formed on the semiconductor chip 110 to expose the edge pads 120 and having a low Young's modulus; metal patterns 140 formed on the lower insulation layer 130 connected to the edge pads 120; an upper insulation layer 150 formed on the lower insulation layer 130 including the metal patterns 140 to partially expose the metal patterns 140 and having either a low or high Young's modulus; and solder balls 160 bonded to the exposed portions of the metal patterns 140. The solder balls 160 are positioned along the center portion of the WLCSP 100. Young's modulus is a term in solid mechanics for quantifying stiffness of a material measured in pascal or gigapascal (as in the SI convention) or in the unit of pressure such as pounds per square inch.
As shown in FIGS. 2A-2D, the WLCSP 100 is mounted on a printed circuit board 200 by the solder balls 160.
In a conventional WLCSP 100, problematic cracks A (see FIG. 2D) appear in the metal patterns 140 when the WLCSP 100 undergoes a thermal cycling test for measuring the characteristic lifetime with respect to temperature changes due to different thermal expansion coefficients of the semiconductor chip 110 and the printed circuit board 200.
Referring to FIG. 2A, as the temperature rises during a thermal cycling test, the printed circuit board 200 bonded to the solder balls 160 of the semiconductor chip 110 is bent toward the semiconductor chip 110. This occurs since the printed circuit board 200 has a higher thermal expansion coefficient than the semiconductor chip 110.
Referring to FIG. 2B, as the high temperature is maintained for a period of time, the printed circuit board 200 bent in the way shown in FIG. 2A returns to its original shape due to “creep” of the solder balls 160. Creep refers to plastic deformation of a material where, for example, the creep in solids occurs at high temperatures where atoms are mobile.
When the temperature falls therafter, as shown in FIG. 2C, the printed circuit board 200 bends away from the semiconductor chip 110. Then, the force applied to the solder balls 160 introduces tensile stresses in the metal patterns 140 connected to the solder balls 160, and as shown in FIG. 2D, the cracks A occur in the metal patterns 140.
The cracks A are formed, because the lower insulation layer 130 having a low Young's modulus and the upper insulation layer 150 having a low or high Young's modulus do not sufficiently reduce the tensile stresses applied to the metal patterns 140 by the solder balls 160. The cracks A in the metal patterns 140 leads to product defects.